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VLSI CALENDAR/2026/INDUSTRY & ACADEMIA

2026-04-20 — 2026-04-22 · PAST EDITION

Industry & academia

DATE 2026 — Design, Automation and Test in Europe

Conference organized by European Design and Automation Association, focused on Design / EDA, Verification, Test / Reliability, Embedded.

Registration

This edition has ended. Explore the archive and future editions.

2026-04-20 → 2026-04-22 · Palazzo della Gran Guardia

Early-bird deadline
Not published
Registration deadline
Not published
Check the organizer’s website ↗
WHEN2026-04-20 — 2026-04-22All-day · time not announced
WHEREPalazzo della Gran Guardia · Verona · ItalyIn person · Conference
FOCUSDesign / EDA · Verification · Test / ReliabilityEuropean Design and Automation Association
TRUSTOFFICIAL SOURCE3 sources · 2026-08-19
EVENT BRIEFING

What to know before DATE 2026 — Design, Automation and Test in Europe

A decision-ready event record: confirmed logistics, attendance path, programme status and a traceable source trail.

EVENT OVERVIEW

DATE 2026 — Design, Automation and Test in Europe is a in person conference organized by European Design and Automation Association. This guide separates confirmed event facts from details the organizer has not yet published, so a visitor can make a practical attendance decision without treating a calendar listing as a promise.

This edition is listed for 2026-04-20–2026-04-22 in Palazzo della Gran Guardia, Verona, Italy. The record is organized around Design / EDA, Verification, Test / Reliability, Embedded; use the official materials for the final programme, speaker line-up and any last-minute venue or registration changes.

FAQ

Event information FAQ

When is DATE 2026 — Design, Automation and Test in Europe?
2026-04-20–2026-04-22. The organizer has not published a time in this record.
Where is DATE 2026 — Design, Automation and Test in Europe?
It is listed for Palazzo della Gran Guardia, Verona, Italy. Recheck the official guide and the map link below for the exact venue scope.
How do I register or attend?
A direct registration URL has not been officially verified in this record. Use the organizer’s page for the latest attendance instructions.
What does the event cover?
The record’s main searchable topics are Design / EDA, Verification, Test / Reliability, Embedded. Use organizer-published materials for the detailed agenda.
How current is this information?
This page preserves 3 sources, including European Design and Automation Association · official event page, and was last reviewed on 2026-08-19. Recheck the official page before booking.
VLSI Korea semiconductor observatory artwork used as an editorial topic image
RELATED EDITORIAL IMAGE · NOT THE EVENTVLSI Korea · VLSI Korea owned editorial artwork · CREDIT ↗
STRUCTURED RECORDdate-2026schema 1.0 · series date · edition 2026
DATE
2026-04-20 — 2026-04-22
TIME
All-day · detailed time not announced
TIME ZONE
Europe/Rome
Central European Time · official
LOCATION
Palazzo della Gran Guardia · Verona · Italy
FORMAT
In person · Conference
CATEGORY
Industry & academia
ORGANIZER
European Design and Automation Association
TOPICS
Design / EDA · Verification · Test / Reliability · Embedded · Hardware Security
VERIFICATION
OFFICIAL SOURCE · official association · 2026-08-19
NEXT REVIEW
2027-02-15
COVERAGE
core
ATTENDEE INTELLIGENCE

Plan this event

Registration, travel, official materials and prior results in one record. We link verified resources only and never invent unpublished details.

01Attend / register

This edition has ended. Use the organizer’s page for the next edition and any published results.

Status: Check official status
02Programme, brochure & results
03Series profile & record stats
Cadence
Cadence not yet verified
First held
Not yet verified
Edition
Edition number not verified
Record series
date
3Event days
3Verified sources
0Listed sessions
4Linked materials
These figures describe record coverage—duration, sources, sessions and materials—not attendee or exhibitor totals.
04Core topics & focus

These tags are searchable focus areas from the event record and VLSI Calendar taxonomy.

Design / EDAVerificationTest / ReliabilityEmbeddedHardware Security
VERIFIED VENUE

Palazzo della Gran Guardia

OPEN IN GOOGLE MAPS ↗

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CFP TIMELINE

Paper & author milestones

EXPLORE ALL CFP ↗
  1. abstract · D, A, T and E tracksResearch paper abstract

    Sunday, 7 September 2025 AoE

    verified date only · checked 2026-08-19OFFICIAL SOURCE ↗
  2. paper · D, A, T and E tracksResearch paper final manuscript

    Sunday, 14 September 2025 AoE

    verified date only · checked 2026-08-19OFFICIAL SOURCE ↗
  3. notification · D, A, T and E tracksResearch paper acceptance notification

    Tuesday, 11 November 2025 AoE

    verified date only · checked 2026-08-19OFFICIAL SOURCE ↗
  4. camera ready · D, A, T and E tracksResearch paper camera-ready manuscript

    Friday, 16 January 2026 AoE

    verified date only · checked 2026-08-19OFFICIAL SOURCE ↗
OFFICIAL PROGRAM

Session schedule

FULL OFFICIAL PROGRAM ↗

The organizer publishes the session timetable on the official program page. VLSI Calendar does not infer unpublished session times.

CONTEXT & HISTORY

Previous editions and VLSI Korea coverage

Verified previous editions, official proceedings, attendee guides, recaps and technical deep dives are linked here.

FULL SERIES HISTORY ↗
PROVENANCE

Field-level source ledger

official confirmed · last checked 2026-08-19
PERSONAL SIGNAL

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COMMUNITY SIGNAL

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